1.3 What is an R10000 Microprocessor?
Execution Pipelines
The three instruction queues can issue (see the Glossary for a definition of issue) one new instruction per cycle to each of the five execution pipelines:
A sixth pipeline, the fetch pipeline, reads and decodes instructions from the instruction cache.
The 64-bit integer pipeline has the following characteristics:
- it has a 16-entry integer instruction queue that dynamically issues instructions
- it has a 64-bit 64-location integer physical register file, with seven read and three write ports (32 logical registers; see register renaming in the Glossary)
- it has two 64-bit arithmetic logic units:
- ALU1 contains an arithmetic-logic unit, shifter, and integer branch comparator
- ALU2 contains an arithmetic-logic unit, integer multiplier, and divider
Load/Store Pipeline
The load/store pipeline has the following characteristics:
64-bit Floating-Point Pipeline
The 64-bit floating-point pipeline has the following characteristics:
- it has a 16-entry instruction queue, with dynamic issue
- it has a 64-bit 64-location floating-point physical register file, with five read and three write ports (32 logical registers)
- it has a 64-bit parallel multiply unit (3-cycle pipeline with 2-cycle latency) which also performs move instructions
- it has a 64-bit add unit (3-cycle pipeline with 2-cycle latency) which handles addition, subtraction, and miscellaneous floating-point operations
- it has separate 64-bit divide and square-root units which can operate concurrently (these units share their issue and completion logic with the floating-point multiplier)
A block diagram of the processor and its interfaces is shown in Figure 1-5, followed by a description of its major logical blocks.
Figure 1-5 Block Diagram of the R10000 Processor
Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96
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